Teaching Videos
(A)Basic HDL Coding Techniques Part-I Xilinx
Duration: 0:29:11
This Basic HDL Coding Techniques, part 1 describes primary coding techniques for FPGAs. It included basic design guidelines that successful FPGA designers follow and explains proper coding techniques for combinatorial and registered logic. Microsoft Windows Media Player 8 or later is required to view this module.
Basic HDL Coding Techniques Part-II Xilinx
Duration: 0:17:10
This Basic HDL Coding Techniques, part 2 describes primary coding techniques for FPGAs. It included basic design guidelines that successful FPGA designers follow, including Finite State Machine design and building pipeline stages. Microsoft Windows Media Player 8 or later is required to view this module.